Field of the Invention
The described technology relates generally to an organic light emitting diode (OLED) display. More particularly, the described technology relates generally to an organic light emitting diode (OLED) display including a gate driver.
Description of the Related Art
Display devices display images, and the organic light emitting diode display among them has been in the spotlight.
The OLED display has a self luminance characteristic and does not require a separate light source, unlike a liquid crystal display (LCD) device, and thus can have reduced thickness and weight. Further, the OLED display represents high quality characteristics of low power consumption, high luminance, and a high reaction speed.
FIG. 1 shows a conventional organic light emitting diode (OLED) display.
As shown in FIG. 1, the conventional organic light emitting diode (OLED) display includes a panel 1, a data driver 3, a gate driver 4, and a pixel (PE).
The pixel (PE) is formed at a crossing region of gate lines (S1 to Sn) and data lines (D1 to Dm). Although not shown, drive power lines can be formed to face the data lines (D1 to Dm). The pixel (PE) is selected to charge a voltage corresponding to a data signal when a gate signal is provided, and it emits light with predetermined luminance in correspondence with the charged voltage.
The data driver 3 supplies a data signal to the data lines (D1 to Dm) when a gate signal is provided from the gate driver 4.
The gate driver 4 sequentially supplies a gate signal to the gate lines (S1 to Sn). Here, the gate driver 4 is formed to be installed on the panel 1 when the pixel (PE) is formed. For this purpose, the gate driver 4 includes an input line 5 and a connecting line 6 provided between an input line 5 and the gate driver 4.
The input line 5 receives a clock signal from a flexible printed circuit (FPC) (not shown). The connecting line 6 is electrically connected to the input line 5, is formed in parallel with the data lines (D1 to Dm), and supplies the clock signal to a stage (not shown) included in the gate driver 4.
Here, the connecting line 6 formed on the panel 1 is provided to be overlapped on the cathode 2. When the cathode 2 is overlapped on the connecting line 6, the connecting line 6 and the cathode 2 form a capacitor to delay the clock signal. In order to overcome such a problem, a plurality of flexible printed circuits (FPCs) 7 are conventionally installed with predetermined intervals so as to be connected to the panel 1, and the clock signal is additionally provided to the connecting line 6 by using the FPCs, which however increases the production cost and thus deteriorates the production yield.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the described technology and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.